This invention relates to programmable logic integrated circuit devices, and more particularly to constructing and operating such devices so that they are compatible with the PCI Special Interest Group""s Peripheral Component Interface (xe2x80x9cPCIxe2x80x9d) bus signaling protocol.
The PCI Special Interest Group""s PCI bus signaling protocol has become widely accepted. At present the PCI standard is a 32 bit bus with a 33 MHZ clock and stringent requirements regarding TCO (time from clock to output: no more than 11 nanoseconds), TCZ (time from clock to high impedance: no more than 11 nanoseconds), TSU (time for setup: no more than 7 nanoseconds), and THD (hold time: no more than 0 nanoseconds). To meet the PCI standard a device must therefore be able to (1) output data very rapidly following a PCI clock signal (TCO), (2) release the PCI bus very rapidly following a PCI clock signal (TCZ), (3) set up to input data very shortly before a PCI clock signal (TSU), and (4) require data to remain present no longer than arrival of a PCI clock signal (THD).
Programmable logic devices have not generally been designed to meet the PCI standard, and it is accordingly difficult or impossible for most such devices to meet that standard. It is therefore difficult or impossible for most programmable logic devices to interface with a PCI bus. This is a limitation on the usefulness of programmable logic devices which is becoming increasingly important as the PCI standard becomes more widely used.
In view of the foregoing, it is an object of this invention to provide programmable logic devices which meet PCI bus standards.
This and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic devices having at least some registers that are relatively closely coupled to data signal input/output pins of the device. For example, there is relatively little signal switching between (1) the input and output terminals of these registers and (2) the data input/output pins of the device. The clock signal input terminals of these registers are also relatively closely coupled to the clock signal input pin of the device (i.e., again there is little or no signal switching between the clock signal input pin of the device and the clock signal input terminals of these registers). These registers preferably supply both output data and output enable signals to tri-state drivers that drive the input/output pins. These characteristics help the device meet the PCI TCO and TCZ requirements. Programmable delay may be provided between input/output pins of the device and the data signal input terminals of adjacent registers to compensate for clock signal skew (e.g., from one side of the device to the other). This helps the device meet the PCI TSU and THD requirements.